Integrated circuit (IC) feature sizes are shrinking steadily into the sub-100 nm range, resulting in increased sensitivity of an IC to on-chip process, voltage, and temperature (PVT) variations. This, in turn, hampers IC performance as well as IC fabrication yields. In general, ICs are fabricated and expected to operate under nominal PVT corner; however, after or during fabrication the PVT parameters inevitably drift from their nominal values. These PVT variations cause various critical circuit performance parameters to deviate from their expected nominal behavior, such as delay, linearity, input/output impedances, static power dissipation, and other performance parameters well known in the art.
On-chip PVT variations can cause fabricated chips to fall short of their performance requirements and significantly lower the overall yield of the chips. Under nominal PVT conditions, a typical IC, such as a Serializer/Deserializer (SerDes) transmitter circuit, exhibits a linear output voltage response. After fabrication however, PVT variations induce non-linearity errors in the output voltage response of the IC. Two main contributors to on-chip variability are changes in process parameters, and changes in operating temperatures. Process parameter variations can occur due to proximity effects in photolithography, non-uniform conditions during deposition, random dopant fluctuations, etc., resulting in fluctuations in parameters such as channel length and width, oxide thickness, dopant concentrations, and threshold voltage. Changes in operating temperatures stem from variations in heat dissipation, leading to a decrease in charge carrier mobility, which in turn causes a direct decrease in current and circuit speed reduction. Moreover, an increase in the operating temperature can also lead to increase in leakage current.
As a result of PVT variations, an IC may require tuning after fabrication. While the effects of process parameters require one-time compensation immediately after the transmitter is fabricated, thermal variations are dependent on the operating environment and as a result the transmitter require an adaptive on-chip circuit that monitors the PVT variations and performs a runtime compensation to minimize the variations. Thus, existing measures fail to address the full scope of the issues raised by PVT variations.